The high level design of the long accumulator chip
H. Fleurkens, R.J.W.T. Tangelder · 1991
The authors discuss an architecture and its high level description of a long accumulator chip suited for the exact calculation of the inner products of floating point numbers. A highly parallel implementation is developed using eight independent adder stations, which add products to two circular long accumulators. A dispatcher schedules each product to the best available station. To validate this architecture and to calculate its performance, a high level description is created. This description is made with ESCHER+, an interactive schematic entry tool with a built-in simulator. The resulting description showed to be the basis for the further implementation of the chip.>