A method to generate tests for combinational logic circuits using an ultrahigh-speed logic simulator
Fumiyasu Hirose, K. Takayama, Nobuaki Kawato · 2003
A method is presented to accelerate test generation, which synthesizes a test-generation circuit S(C, F) that combines the original combinational circuit C (modified by programmable faults F) and peripheral circuits that automatically generate a test of C. The test patterns are generated by searching the inputs to expose faults to the outputs using an ultrahigh-speed simulator (SP).>