High performance firmware architecture for FIR filtering in DSP processors
Sebastiano Scarpaci, Andrea Suardi, A. Geraci, G. Ripamonti · IEEE Symposium Conference Record Nuclear Science 2004. · 2007
The paper presents a technique for implementing finite impulse response (FIR) filtering in last generation digital signal processors (DSP), which has been specifically designed and developed. Thanks to a fully assembler coded firmware that exploits at best the device resources, a maximum parallel data processing architecture can be implemented that considerably improves the filtering process efficiency with respect to standard solutions that are based on C language firmware codes.