Advanced ternary CAM circuits on 0.13 μm logic process technology
Alan Roth, D. Foss, Ray J. McKenzie, Dan Perry · 2004
An embedded ternary CAM macro derived from a 9M stand alone part with die size of 148 mm/sup 2/ uses a novel 3.542 /spl mu/m/sup 2/ SRAM half-cell on a standard 0.13 /spl mu/m logic process. In the embedded form it takes 13 mm/sup 2//Mbit. The macro achieves 166 M-searches/s with low power, under 0.5 W/Mbit. A divided match line greatly reduces the power inherent in parallel searches. Prioritized multiple match output, status bit functions, and on-the-fly variable word width are included.