Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits
Martin Rozkovec · 2008
This paper presents the BIST architecture for SoPC circuits. DyRespin reuses scan chains in embedded cores for decompression of highly compressed test vectors. The test access mechanism (TAM) for scan chain connections is implemented as a reconfigurable module. We reuse the switching logic in the interconnection matrix in order to save logic resources. For circuits with higher number of scan chains, the reconfigurable TAM is much more effective than the multiplexer based TAM, comparing usage of the logic resources and clock speeds.