A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications
Adnan Suleiman, Hani H. Saleh, Adel Hussein, David Akopian · 2008
The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024-point FFT with 2 processing elements using 45 nm process technology, including area, timing, power and place-and-route results.