SAT-based ATPG testing of inter- and intra-gate bridging faults
Tom Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada · 2009
This paper presents an ATPG framework for IDDQ testing of both intra- and inter-gate bridging faults. The framework integrates random simulation and a deterministic stage using Boolean SATisfiability (SAT) as the underlying engine. This decides whether a fault is testable or untestable. In this way, we conduct an exact search for test patterns for IDDQ testing of both intra- and inter-gate bridging fault detection.