A Design of Multi-threaded Shader Processor with Dual-Phase Pipeline Architecture
Kwang-Yeob Lee, Tae-Ryoung Park, Jae-Chang Kwak, Yong-Seo Koo · 2009
In this paper, dual-phase pipeline architecture and variable length instructions of a shader processor are proposed. The dual-phase pipeline architecture achieves a performance of dual core using a single core, and a parallelism of GP-GPU to accelerate graphic operations. For simplifying hardware, the register optimization is proposed. The variable length instructions are designed for efficient executions with less memory. Various pipeline hazards are resolved by a multi-threaded method. The proposed processor supports OpenGL ES 2.0. It has a size of 0.13Mlogic and shows the performance of 16.6MVertices/s, and 33.3MPixels/s.