Implementation Of Bayesian Network In FPGA Circuit
Zbigniew Kulesza, Wojciech Tylman · 2006
The paper presents a novel approach to the implementation of Bayesian network - an implementation in an FPGA circuit. The opportunities and problems connected with the parallel-processing approach of the FPGA circuit are discussed. Modifications of the computation algorithm that are needed due to limited computational capabilities are described. Details of the construction of the main computational blocks are also depicted