Low Power Test
Swapnil Bahl, Ranadhir Sarkar, A. Garg · 2008
The power consumed during test mode is higher than the functional mode and becomes significantly higher for low power devices. The increased heat can result in chip burnouts and reliability issues due to electro-migration. This poster presents the reasons for higher power consumption, its consequences, and various solutions, both at hardware and software level, for reducing the overall test mode power. It also highlights the benefits, costs and practicability by applying it on few ST SoCs.