POWER REDUCTION THROUGH MERGED FLIP-FLOPS
K. Abinaya · International Journal of Research in Engineering and Technology · 2014
Optimization of power is always one of the most important design objectives in the modern ICs.In that maximum power is consumed by clock, the power is reduced using multi-bit flip-flops.This process is achieved by merging some of the flip-flops used in the circuit, based on the timing and capacity constraints.Merging of flip-flops is done with help of co-ordination transformation and combination table.We can achieve better area minimization, wire length reduction and power reduction by 75%.The experimental results are shown through the above parameter achievements.