A configurable multiprocessor system for DSP behavioral simulation
W. Koh, Alfred Yeung, Phu Hoang, Jan M. Rabaey · 2003
SMART, a multiprocessor architecture optimized for real-time behavioral simulation of digital signal processing (DSP) systems, is presented. The first prototype, currently under development, contains eight processors (peak 160 MFLOPS). The number of processors will be increased to 64 (peak 1.28 GFLOPS) in the future. The SMART system features a configurable bus and bypass units to improve the bandwidth of a single shared bus by taking advantage of the local communication between processors. Write queues and a distributed shared-memory system are provided to overlap the interprocessor communication with the processor computation, thereby making interprocessor communication delays almost invisible. Barrier synchronization, which is frequently used in DSP algorithms, is supported by hardware to yield low synchronization overhead.>