A 50ns floating-point signal processor VLSI
Takao Kaneko, H. Yamauchi, Atsushi Iwata · 2005
A high-speed programmable digital signal processor VLSI with an 18-bit floating-point architecture and a 32-bit micro-instruction has been fabricated using 1.2µm CMOS technology. The device contains 280k transistors and executes every floating-point operation within a 50ns machine-cycle. The architecture differs from that of the DSSP (Digital Speech Signal Processor), reported previously, in its high-speed parallel pipeline structure, 16k-byte on-chip micro-program ROM, floating-point ALU capable of 50ns operation, as well as in its enhanced DSP instruction set.