Advanced instruction set architectures for reducing program memory usage in a DSP processor
P. Simonen, K. Saastamoinen, Mika Kuulusa, Jari Nurmi · 2003
On-chip memories can consume multiple times the area of a processor core, thus affecting to the chip costs dramatically. In this paper three approaches for reducing program memory footprint in a DSP processor are analyzed: fully 16-bit and two versions of mixed 16/32-bit instruction encodings. A separate decompression logic is implemented between memory and core, so the 32-bit processor core remained unchanged. Compared to the original 32-bit instruction set, the fully 16-bit ISA (Instruction Set Architecture) eliminates 22% of the program memory footprint with a 1.55 times the original runtime. Mixed 16/32-bit ISAs achieve virtually same memory size, but with a faster runtime of 1.29 times the original at best.