A 553 K-transistor LISP processor chip
P. Bosshart, C. R. Hewes, M.D. Ales, Meng‐Chou Chang, K.K. Chau, K. Fasham, C.C. Hoac, Theodore W. Houston, V. Kalyan, S.L. Lusky, Shivaling S. Mahant-Shetti, Douglas J. Matzke, Kosha Ruparel, J. Sexton, Ching-Hao Shaw, T. Shridhar, Don Stark, A.L. Lee · IEEE Journal of Solid-State Circuits · 1987
The authors describe a LISP microprocessor which includes over 550 K transistors, has 114 K of on-chip RAM, and runs instructions in a single 30-ns clock cycle. The chip is implemented in 1.25-/spl mu/m double-level-metal (DLM) CMOS, has 224 pins, and is packaged in a custom pin-grid array. The microinstruction and macroinstruction sets of this chip are compatible with an existing LISP processor. An extensive discussion of test features designed into the processor chip is given.