Low complexity sequential normal basis multipliers over GF(2/sup m/)
Arash Reyhani-Masoleh, M.A. Hasan · 2004
For efficient hardware implementation of finite field arithmetic units, the use of a normal basis is advantageous. Two architectures for multipliers over the finite field GF(2/sup m/) are proposed. Both of these multipliers are of sequential type - after receiving the coordinates of the two input field elements, they go through m iterations (or clock cycles) to finally yield all the coordinates of the product in parallel. These multipliers are highly area efficient and require fewer number of logic gates even when compared with the most area efficient multiplier available in the open literature. This makes the proposed multipliers suitable for applications where the value of m is large but space is of concern, e.g., resource constrained cryptographic systems. Additionally, the AND gate count for one of the multipliers is /spl lfloor/m/2/spl rfloor/+1 only. This implies that if the multiplication over GF(2/sup m/) is performed using a suitable subfield GF(2/sup n/), where n>1 and n|m, then the corresponding multiplier architecture will yield a highly efficient digit or word serial multiplier.