Fault grading the Intel 80486
N.S. Gollakota, A. Zaidi · 2002
The fault grading methodology used for developing test vectors for the 80486 microprocessor is described. The methodology included developing a simulation model for logic verification and tests for 100% toggle coverage at the RTL level, completing logic verification, developing the fault lists and optimizing them by fault collapsing, performing fault simulation on a sample of faults and in parallel simultaneously identifying/eliminating undetectable faults, performing fault simulations on complete fault lists for blocks which have high initial fault coverage, and developing new tests for blocks with low coverage. The practical issues and bottlenecks involved in quickly achieving a high fault coverage are identified. Built-in self-test features which provided a high initial fault coverage are highlighted.>