Reconfigurable FPGA-Based Hardware Accelerator for Embedded DSP
G. Rubin, Mirosław Omieljanowicz, Alexander Alexandrovich Petrovsky · 2007
This paper presents reconfigurable FPGA-based hardware accelerator for embedded DSP. At first the principle of shared-memory based processor are shown and then specific universal balanced architecture is proposed. An example of processor for TVDFT on the given accelerator is also given. Implementation of multiplier and adder based on the serial arithmetic are included as processor elements.