Microarchitectural synthesis of VLSI designs with high test concurrency
Ian G. Harris, Alex Orailoğlu · 1994
The testability of a VLSI design is strongly aected by its register-transfer level (RTL) structure.Since the high-level synthesis process determines the RTL structure, it is necessary to consider testability during high-level synthesis.A synthesis system composed of scheduling and binding components minimizes the number of hardware sharing con icts between tests in the test schedule.Novel test con ict estimates are used to direct the synthesis process.The test con ict estimation is based on examination of the in terconnect structure of the partial design state during synthesis.Test con ict estimates enable our synthesis system to select design options which increase test concurrency, thereby decreasing test time.Experimen tal results show that designs generated by this approach are testable in a highly concurrent manner.