Design of programmable NoC router architecture on FPGA for multi-cluster NoCs
Henrique Cota de Freitas, Tatiana G. S. dos Santos, Philippe O. A. Navaux · Electronics Letters · 2008
The next generations of massive, parallel and reconfigurable multi-cluster chips need performance and flexibility, requiring new communication schemes. According to this scenario, a programmable router architecture for networks-on-chips is presented. Results indicate that the proposed router has low area occupation, low power consumption and a high data throughput.