Overcoming the serial logic simulation bottleneck in parallel fault simulation
E.M. Rudmocl, Janak H. Patel · 2002
We propose a new approach to parallelizing fault simulation in which the test set is partitioned among the available processors. The approach can be used for any of the sequential circuit fault simulation algorithms commonly used, and it can be implemented on various different parallel architectures. This approach for the first time overcomes the limitations of serial logic simulation. In addition, the excessive redundant computations required in the traditional fault-partitioning approach are also considerably reduced. Significant improvements in speedup were observed as compared to previous approaches. An average speedup of 5.7 was obtained for test set partitioning over 10 processors for the benchmark circuits studied. Although pessimistic fault coverage may be reported in some cases, the proposed approach was found to be very accurate for the circuits studied.