HD/sup 2/BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs
Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, P. Prinetto, F. Ricciato, M. Spadari, Y. Zorian · 2002
Proposes HD/sup 2/BIST, a complete hierarchical framework for BIST scheduling, data patterns delivering, and diagnosis of a complex system including embedded cores with different test requirements as full scan cores, partial scan cores, or BIST-ready cores. The main goal of HD/sup 2/BIST is to maximize and simplify the reuse of the built-in test architectures, giving the chip designer the highest flexibility in planning the overall SoC test strategy. HD/sup 2/BIST defines a test access method able to provide a direct "virtual" access to each core of the system, and can be conceptually considered as a powerful complement to the P1500 standard, whose main target is to make the test interface of each core independent from the vendor.