An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions
Masahiro Murakawa, Takehiko Adachi, Y. Niino, Yuji Kasai, Eiichi Takahashi, K. Takasuka, Takuya Higuchi · IEEE Journal of Solid-State Circuits · 2003
We have developed a large-scale integration (LSI) for Gm-C intermediate frequency (IF) filters, attaining a 63% reduction in filter area, a 26% reduction in power dissipation, compared with existing commercial products using the same process technology and filter topology, and a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm - an efficient AI technique for difficult optimization problems. Our calibration method, which can be applied to a wide variety of analog circuits, leads to cost reductions and the efficient implementation of analog LSIs.