A design of parallel matched filter with low calculation cost
Takehiko Sugawara, Yoshikazu Miyanaga · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
In this report, we propose a new architecture of a matched filter used in CDMA systems. The new architecture reduces the calculation cost of required data correlation significantly. Since the calculation of the correlation into a matched filter becomes quite large amount of operation, the large circuit scale and the high power consumption happen on a mobile system. Accordingly the low calculation cost has been demanded. The proposed matched filter applies two step correlation algorithm into the data processing. Therefore, the amount of the operation can be decreased. In addition, it is expected that the operation speed and the power consumption of a matched filter circuit module are improved.