False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation
Jing-Jia Liou, Angela Krstić, Li-C. Wang, Kwang-Ting Tim Cheng · Proceedings - ACM IEEE Design Automation Conference · 2002
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool can characterize statistical circuit delay distribution for the entire circuit and produce a set of true critical paths.