Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor
M. Simone, D. Tovey, A. Essen, Atsushi Ike, A. Krishnamoorthy, T. Maruyama, N. Patkar, M. Ramaswami, Michael C. Shebanow, V. Thirumalaiswamy · 1995
The implementation of a superscalar, speculative execution SPARC-V9 microprocessor incorporating Restricted Data Flow principles required many design trade-offs. Consideration was given to both performance and cost. Performance is largely a function of cycle time and instructions executed per cycle while cost is primarily a function of die area. Here we describe our Restricted Data Flow implementation and the means with which we arrived at its configuration. Future semiconductor technology advances will allow these trade-offs to be relaxed and higher performance Restricted Data Flow machines to be built.