A full-adder based reconfigurable architecture for fine grain applications: ADAPTO
G.C. Cardarilli, Luca Di Nunzio, Marco Re · 2008
Microprocessor and DSP are optimized to perform operations on data having the same size of native wordlength. Their performances decrease when shorter data must be processed. In fact, operations on a short data have the same complexity native wordlength data and data resources aren’t fully exploited. Recently different solutions have been proposed to overcome this problem. Great attention has been posed on architectures based on a main processor supported by a Reconfigurable Unit (RU) - typically based on LUTs- used as coprocessor. In [1]we presented ADAPTO (Adder-based Dynamic Architecture for Processing Tailored Operators) a new reconfigurable architecture that replacing LUTs with another computational element and using a simplified interconnect network allows, in one clock cycle of the main microprocessor, both hardware reconfiguration and instruction execution. In this paper we present a modified version of ADAPTO that achieves more flexibility.