System level fault simulation
Pablo Sánchez, I. Hidalgo · 2002
Gate level fault simulation has been a typical step in the ASIC design process but it cannot be used for real hardware/software systems in which there are multiple boards and chips, several test strategies, complex embedded systems in ASICs and different test procedures (hardware test pattern generation, software programs for hardware tests, etc.). This paper proposes a new methodology bared on VHDL which covers the new fault simulation demands of real digital systems.