Memory latency reduction using an address prediction buffer
A. Billingsley, Douglas J. Fouts · 2002
A novel approach to improving memory system performance is the use of a memory prediction buffer (MPB). The MPB is inserted between the cache and main memory. The MPB predicts the next cache-miss address and prefetches the data. The use of an MPB in a computer system is shown to decrease memory latency and increase system performance. The MPB outperforms prefetch always strategies by allowing addressing in the up and down direction. In addition, the MPB does not contribute to pollution of the cache. Only demand information is taken from the MPB to the cache. The implementation of a MPB is less expensive than a next-level cache and delivers a comparable performance enhancement.>