The application of yield modelling to the WASP parallel processing architecture
N.G. Sheridan, Hamid Bolouri, R.M. Lea · 2003
The authors address yield modeling considerations and their impact upon the floorplanning and defect tolerance strategies of the WSI Associative String Processor (WASP) architecture. A fully parameterized, detailed yield model for the WASP architecture has been presented previously. This yield model has been developed further and applied to the various design options for future WASP devices. Using the improved model, the impact of these design options on the yield of WASP devices is assessed, leading to a set of recommendations as the optimum WASP floorplan.>