CMOS design for improved IC testability
Michele Favalli, Piero Olivo, M. Damiani, B. Riccò · 2003
Novel design-for-testability schemes are suggested to improve the detectability of transistor stuck-on faults, bridgings, and gate oxide shorts in CMOS digital circuits, with limited extra hardware and minimum degradation of circuit performance. One of the techniques makes analog faults detectable by observing the circuit outputs just as for stuck-ats. Also described is a technique in which the gates are modified with the insertion of n-channel FETs whose drains are the input of a ratioed NOR testing logic realized with n-channel drivers and a single resistive p-channel pull-up device.>