ALLOCATION AND ASSIGNMENT IN HIGH-LEVEL SYNTHESIS FOR SELF-TESTABLE DATA PATHS
L.J. Avra · 2005
This paper describes a technique and program for automatically synthesizing a self-testable data path structure given a scheduled data flow description of a design. The resulting data path structure is combinationally self-testable when the registers are reconfigured as either pseudo-random pattern generators or parallel signature analyzers. The synthesis procedure consists of first mapping the data flow description onto a register conflict graph. The nodes of the graph are then colored using a node coloring algorithm that is guided by design implementation costs such as interconnection area and multiplexer size. Finally, the colored graph is mapped to hardware. A simple constraint imposed on the conflicl. graph guarantees combinational self-testability of the data path. In addition, new methods for mapping the data flow description to the conflict graph are incorporated to allow the procedure maximum flexibility in synthesizing arr efficient hardware implementation.