Implementation of RISC-Based Architecture for Low power applications
Shaik Afroz · IOSR Journal of Electrical and Electronics Engineering · 2013
This paper explains the design of a simple RISC processor and procedure for simulating it.A Reduced Instruction Set compiler (RISC) is a microprocessor that had been designed to perform a small set of instructions, with the aim of increasing the overall speed of the processor along with reducing the power consuming while executing the instruction.The RISC architecture follows the philosophy that one instruction should be performed every cycle.This work presents the design and implementation of a 32 bit RISC soft core processor intended for computer architecture introduction considered to be an effective solution for computer comprehension.The idea of this project was to create a microprocessor as a building block in VHDL than later easily can be included in a larger design.It will be useful in systems where a problem is easy to solve in software but hard to solve with control logic.A state machine dedicated to the function can of course replace the microprocessor and associated software.However at a high level of complexity it is easier to implement the function in software.In this project Modelsim is used for logical verification and further synthesizing is carried on Xilinx-ISE tool.To perform the power analysis the Xilinx xpower analyzer is used.