Fast pipelined multipliers for bit-serial complex numbers
Luca Breveglieri, Vincenzo Piuri, Donatella Sciuto · 2002
A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture.>