A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch
A. Mu, B. Chia, Srinivas Kondapalli, Cheol Hea Koo, J. Larson, Luong N. Nguyen, R. Sastry, Yoshihiko Satsukawa, Hsi-Ching Shih, Thomas Wicki, Chia‐Ming Wu, Kenan Yu, Xiaoyang Zhang · 2002
The HAL router chip is a 285 MHz 6-port plesiochronous packet-switched routing chip with non-blocking cross-bar switch. It combines very high bandwidth (4.5 GByte/s per port, 27 GByte/s total raw bandwidth), low fall-through latency (32 ns), no internal blocking, three arbitration priorities with in-order delivery, a flexible source routing scheme, virtual-cut-through routing, and robust reverse flow control.