A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register
Z.M. Darus, I. Ahmed, Liakot Ali · 2002
This paper presents the design of a low cost, test processor ASIC chip implementing multiple seed, multiple polynomial linear feedback shift register (MPMSLFSR). User programmable seed and feedback connection can be set in the pattern generator of the chip to improve fault coverage. The ASIC also supports scan-path testing. It can also be used to design external IC tester.