A technique for generating efficient simulators
Przemyslaw Bakowski, Jean-Luc Dubois, Adam Pawlak · 2002
A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.>