SYSTAT: a system level timing verifier
S. Hojat, Mahboobeh Bonyadi, Shi Yong, S. Bonyadi · 2002
Timing verification is one of the most critical steps in the design of digital systems to ensure that the system functions correctly at an expected speed. SYSTAT (SYStem level Timing Analysis Tool) is a static timing verification tool which was developed to address the advanced needs and requirements of engineers at NCR E&M San Diego. An overview is presented of some of the advanced algorithms and techniques used within SYSTAT. Features that are being added to SYSTAT are summarized.>