Active timing multilevel fault-simulation with switch-level accuracy
Wilku B. Meyer, Raúl Camposano · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1995
This paper describes SATISFAULT, a new hierarchical multilevel fault simulator with switch-level fault models and switch-level accuracy. SATISFAULT's intelligent scheduling mechanism switches between the abstraction levels to force simulation at the highest, thus fastest, possible level of abstraction without losing switch-level accuracy. The simulation algorithm is based on single fault-propagation for active faults. It deals with multiple abstraction levels and supports the inertial delay model. As a result, even large circuits may be fault-simulated accurately with all faults injected at the switch-level. Complete fault-simulation of all transistors stuck-on and stuck-open of circuits up to 105000 transistors including faults inside flip-flops is possible in reasonable time. In addition, SATISFAULT is also capable of simulating bridging faults for IddQ detectability.>