A VLSI Implementation of Lfsr For Test Pattern With Bist Techniques
Sathyanathan.A Sathyanathan.A · International Journal of Scientific Research · 2012
This paper presents a VLSI implementation of LFSR for Test pattern with BIST techniques with Naive, LAT and TePLAT algorithms. LFSR 10 is specified by generator polynomial over Galois Field. This paper examines a new algorithm called as Term Preserving Look Ahead Transformations (TePLAT). It converts bit serial algorithm to bit parallel algo- rithm with overhead. For bit parallelism the used technique is Loop Unrolling. LFSR 10is designed on various algorithms such as LAT, TePLAT. Hardware of LFSR 10 is implemented on Xilinx Spartan 3E.Simulation tool used for this LFSR 10 is Xilinx ISE simulator and this is modeled in Verilog HDL. Mainly bit level parallelism technique is used for speed up the process.