On the efficiency of formal synthesis-experimental results
Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1999
Formal synthesis has become an interesting alternative to postsynthesis verification. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the efficiency of the underlying rules. This paper gives a case study about the complexity of formal synthesis programs. Experiments with two realistic-sized benchmark circuits were performed using the formal synthesis system HASH. HASH provides means for representing and transforming circuits in a secure and logically sound manner. Furthermore, arbitrary synthesis procedures can be invoked to achieve high quality of designs. In this paper, the implementation of a formal scheduling step is used to illustrate efficiency considerations related to formal synthesis.