VERTEX: VERification of Transistor-level circuits based on model EXtraction
John Moondanos, Jalal A. Wehbeh, J.A. Abrahamn, Daniel G. Saab · 2002
VERTEX, a program that performs formal verification of synchronous sequential circuits that are characterized at the transistor-level is described. Additionally, VERTEX can compare gate-level designs or Boolean specifications against their switch-level implementations. VERTEX verifies a hardware design by employing novel techniques to extract the relevant state variables of a switch-level circuit and to compare the finite state machine descriptions of hardware designs based on formal methods for the verification of sequential circuits.>