A highly integrated 40-MIPS (peak) 64-b RISC microprocessor
Jiro Miyake, T. Maeda, Y. Nishimichi, J. Katsura, T. Taniguchi, S. Yamaguchi, Hisakazu Edamatsu, S. Watari, Yuji Takagi, Kosuke Tsuji, Shigeo Kuninobu, S. Cox, D. Duschatko, Doug MacGregor · IEEE Journal of Solid-State Circuits · 1990
A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit.>