Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor
Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang · 2008
Network-on-Chip (NoC) is a promising solution for efficient interconnection between processor cores in Chip-Multi-Processor (CMP). This paper is focusing on the energy-efficient design of buffers, a group of the most important components in NoC. From our investigation, an overwhelming majority of "zero" is contained in the packets transmitting in NoC for CMP. A zero-efficient buffer design is proposed as well as the error control scheme. Compared with conventional design, up to 43% energy consumption can be saved. We use a 90nm CMOS process in our simulation.