Selecting a well distributed hard case test suite for IEEE standard floating point division
Lee D. McFearin, David W. Matula · 2002
We investigate two sets of hard to round p/spl times/p bit fractions arising from division of a normalized p bit floating point dividend by a normalized p bit floating point divisor. These sets can be characterized by the p/spl times/p bit fraction's quotient bit string, beginning with or just after the round bit, having the maximum number (p-1) of repeating like bits, specifically 00...01 or 11:..10 for the directed rounding "RD-hard" set and 100...01 or 011...10 for the round-to-nearest "RN-hard" set. We describe an algorithm for generating both the RD-hard and RN-hard sets in order of quotient value for any p, and use properties of fractions and continued fractions to characterize the distribution of these sets based on numerator, denominator, and quotient values. As a practical chip test example we summarize test runs showing our hard to round test suites are several orders of magnitude more efficient than random testing in finding erroneous quotients computed by the 1993 Pentium Processor having the well known fdiv flaw.