Area-efficient memory-based architecture for FFT processing
Sang-Chul Moon, In‐Cheol Park · 2003
In this paper, we propose a new area-efficient parallel architecture to calculate 2/sup n/-point FFT. The proposed architecture is based on the radix-4 Cooley-Tukey algorithm, and consists of four complex multipliers, eight complex adders, and four RAMs each of which is partitioned into two banks. The implemented FFT processor can calculate 2 K/4 K/8 K-point complex FFT in 28.2 /spl mu/s/62.0 /spl mu/s/135.2 /spl mu/s at 91 MHz, respectively.