Execution of neutral network algorithms on an array of bit-serial processors
Bertil Svensson, Tomas Nordström · 2002
A general model of an array of bit-serial processors is given, and the mapping of neural network models on such an array is demonstrated. The approach maps a neuron on each processing element and makes communicating between a node and any other node possible by connection weight matrices. The required communication structure is very simple. The bit-serial approach allows tradeoffs between speed and precision, even dynamically. Performance figures are given. A bit-serial multiplier is an important part of the design. Implementation aspects are discussed, and it is shown that a one-board realization of 1024-processor system is feasible.>