Chip-Package Co-Implementation of a Triple DES Processor
T. Schaffer, A.W. Glaser, Paul D. Franzon · IEEE Transactions on Advanced Packaging · 2004
This paper describes the design and implementation of a dedicated data encryption standard (DES) processor. The processor consists of three 0.6 /spl mu/m complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) mounted on a single MCM-D thin-film substrate. Each chip can operate on an individual data stream, or the three can be cascaded to implement the so-called "triple-DES" (3DES) function for increased security. Measurements show 3DES operation at 110 MHz, which translates to a throughput of over 7 Gb/s, the highest reported 3DES throughput to date. System features which contribute to this throughput are the use of area-array (flip-chip) input/output (I/O) and global IC power/ground/clock distribution in the MCM package. In this case, package-level distribution reduced clock skew by 150 ps, and reduced the chip area required for power distribution by 20%. This paper also includes measurements of switching noise of the MCM's V/sub dd/ plane and how it correlates with a simple model of the system power distribution.