An efficient implementation of fair load balancing over multi-CPU SOC architectures
George Kornaros, Theofanis G. Orphanoudakis, N.A. Zervos · 2003
Emerging applications for network processors require increased number of processing resources. This paper introduces a novel system to load balance the scheduled traffic over multiple processing cores maintaining in-order service. It is conceived in the framework of today's demanding network processors, but it is obviously applied to every multiprocessor platform. The focus of the paper is on an efficient load-balancer supported by a high speed dual-pipeline engine tailored to operate at line rates over OC-192/10Gbps. Finally, an optimized implementation is presented occupying 1.34 mm/sup 2/ using a standard 0.18 /spl mu/m CMOS technology, while supporting 59.5 Million network packets per second.