A high-performance CMOS 32-bit parallel CRC engine
Richard F. Hobson, K. L. Cheung · IEEE Journal of Solid-State Circuits · 1999
Design highlights for a 32-bit parallel cyclic redundancy check (CRC) generator engine are presented. In a 0.8-/spl mu/m three-layer-metal CMOS process, the engine could handle about 5 Gbps data throughput. A compact layout is achieved by predecoding eight groups of four bits followed by performing a binary tree reduction on nets that are sorted by fanout. There are six gate delays plus a single-phase clock edge-triggered register.